Design And Implementation OF a PLL Using VHDL AMS Project Report

Analog/mixed signal design is seeing a pattern shift in design flow from bottom-up to top-down, which makes the realization of complex designs more convenient and feasible. Analog HDLs and behavioral libraries enable system designers to quickly write a block-level system model that can easily be simulated to optimize chip performance early in the design cycle. Because it’s written in a standard HDL, this system design can be employed as a live specification to pass down to the transistor-level designer or out to a design subcontractor in a language that they and their tools will understand. Once in the hands of the transistor-level designers, each block can be logically decomposed and simulated, in increasing levels of detail, until the final transistor design is reached. Such a methodical approach can shave weeks or months off of the design cycle, helping companies meet their time-to-market deadlines.

Description

To gain a thorough understanding of transistor-level behavior, any differences between transistor-level design and its upper-level behavioral model need to be closely examined. This is the ideal time to calibrate the model to the transistor design. If the upper-level model is a library part, the designer can use the built-in test bench to automatically stimulate and characterize the transistor-level design. If the upper-level model is a custom model, the designer can build a test bench and/or use an optimization tool, to match the model to the transistor-level behavior. Any differences must be understood completely and resolved. Once the analog and digital designs are complete, they must be tested to verify that they work together before going to layout and Fabrication.